资源列表
cnt_fry
- 本程序功能是由VHDL语言实现对频率的测量，然后用数码管进行显示-The program features by the VHDL language to achieve the frequency of measurement, and then use the digital tube display
Reg16
- 寄存器组的原理实现，16位，Verilog语言实现，仿真成功。-Register realization of the principle, 16, Verilog language, the simulation successfully.
S8_SETPMOTO
- cyclone II EP2C8 对步进电机的基本操作-cyclone II EP2C8 the basic operation of the stepper motor
Fix-and-Floating-1024k--using-CPPFFT
- Fix and Floating Point 1024k FFT using c-Fix and Floating Point 1024k FFT using c++
lcd_palace
- lcd 显示 welcome it s for lcd 。show welcome it s used vhdl language。c++ also，if you cannot understand please inform me。it s important when you use it。-it s for lcd 。show welcome it s used vhdl language。c++ also，if you cannot understand please inform
JYSZCCLBQ
- 简易数字滤波器的设计 基于EDA语言 开发平台较广-Simple digital filter design language development platform based on the broader EDA
Verilog FSM
- 本实验介绍了FSM状态机的特点 应用等 其中源代码相当的详细，适合初学人群
clock
- 多功能数字钟的verilog程序，可用于年月日的记时和显示。-Multi-function digital clock verilog procedures, can be used for date time and display.
johnson
- johnson计数一个比较高级的跑马灯可以控制灯的方向-Johnson count is a more advanced Marquee can control the direction of the light
FPGA-dsp-motor-control
- 基于FPGA的LAMOST多电机控制驱动系统-Based on the FPGA LAMOST motor control and drive system
IIR-DIGITAL-NOTCH-FILTER
- IIR数字陷波器的设计文档，可以作为设计陷波器的参考文献-IIR digital notch filter designing document,it can be used as references to design notch filter
EDA1
- 完成一位二进制全减器的设计，采用文本输入法分别实现，分层设计，底层采用半加器和逻辑门实现。-Completion of a binary full subtracter design, implementation, respectively, using the text input method, hierarchical design, are based on half adder and logic gates.