资源列表
ask
- ASK调制与解调VHDL程序及仿真，完全实现，详细！-ASK modulation and demodulation process and VHDL, and simulation, fully realized, in detail!
ASK
- 基于VHDL硬件描述语言，对基带信号进行ASK振幅调制-VHDL hardware descr iption language based on the ASK baseband amplitude modulation signal
Example-4-8
- always模块的敏感表为电平敏感信号的组合逻辑电路 这种形式的组合逻辑电路应用非常广泛，如果不考虑代码的复杂性，几乎任何组合逻辑电路都可以用这种方式建模。always模块的敏感表为所有判定条件和输入信号，请读者在使用这种结构描述组合逻辑时，一定要将敏感表写完整。在always模块中可以使用if…else…、case、 for循环等各种RTL关键字结构 assign等语句描述的组合逻辑电路 这种形式的组合逻辑电路适用于描述那些相对简单的组合逻辑，信号一般被定义为wire型，常用
lianxi
- 该程序是用VHDL语言实现一个四位整数的加法器代码-adder
PLDESIGNQA91
- 这是硬件逻辑设计的一份参考资料，总结了目前主流FPGA供应商设计的注意事项。-This is a hardware logic design of a reference, summed up the current mainstream FPGA vendor design for attention.
8.9-ASK-debug-VHDL-program
- 基于VHDL硬件描述语言，对基带信号进行ASK调制-VHDL hardware descr iption language based on ASK modulation baseband signal
ASK--vhdl
- ASK调制与解调VHDL程序及仿真 ask的调制解调使用VHDL语言-ASK modulation and demodulation process and VHDL simulation ask modulation and demodulation using VHDL language
ASK
- ASK调制与解调的VHDL源程序 附带仿真-ASK modulation and demodulation of the VHDL source code with simulation
11
- ASK调制与解调系统VHDL程序及仿真-ASK modulation and demodulation system and simulation of VHDL procedures
multiplier
- Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support
ALU
- this verilog code is alu. which is perform addition and sub,mul,div
degree_of_distortion
- 基于FPGA开发板和AD/DA板设计了一个数字化失真度测量仪(A digital distortion measuring instrument is designed based on FPGA development board and AD/DA board.)