资源列表
jtd
- 本实验要完成任务就是设计一个简单的交通灯控制器，交通灯显示用实验箱的交通灯模块和七段码管中的任意两个来显示。系统时钟选择时钟模块的1KHz 时钟，黄灯闪烁时钟要求为2Hz，七段码管的时间显示为1Hz 脉冲，即每1s 中递减一次，在显示时间小于3 秒的时候，通车方向的黄灯以2Hz的频率闪烁。系统中用S1 按键进行复位。-To complete the tasks in this experiment is to design a simple traffic light controller, t
eprom_samsat_560_ok_24c16
- sk24c16e eeprom samsat 560
VHDLbasic_cal
- VHDL的加、减、乘、比较等基本运算的源代码-VHDL add, subtract, multiply, compare the source code of the basic operations
eetop.cn_数字IC面试题__8.3整理
- 数字ic面试题目以及一些面试的经验，帮助ic设计工作者找到人生中的第一份工作(Digital IC interview)
filter
- 在DE2-70上运行的程序，程序是一个低通滤波器，滤波器用VHDL语言实现，已经过验证，可以放心使用。-DE2-70 to run the program, the program is a low-pass filter, the filter using VHDL, has been verified and is safe to use.
led_display
- 数码管的静态显示，本代码仅供交流学习，未经同意不得用于其它商业用途。-hao hao
Double-byte-adder-BCD-code
- 将以片内RAM 30H 为起始地址的双字节BCD码 30H和40H为起始地址的双字节BCD码相加，结果放在50H和51H中，程序结束-Will be in RAM30H for the starting address of the double byte BCD code 30H and 40H for the starting address of the double byte BCD code phase, results in 50H and 51H, end of program.
EXA01
- 一个关于VHDL的cpld开发实验程序，通过运用max+plus 运行程序，实现实验相关功能 -VHDL CPLD on the development of experimental procedures, through the use of max+ plus run the program, the experimental implementation-related features
vhdl-arm-core
- 用vhdl语言实现arm内核，压缩包中有19个代码共同组成这个arm内核，程序比较大，应用时要注意那个代码是顶层实体。用quartus2软件即可打开仿真。-Vhdl language used arm core, compressed package code of 19 common core component of this arm, procedures, and application code should be noted that top-level entity. Used t
counter
- measure the time period
Key7.1SP1(b178)
- Qutuas II v7.1的key_gen 对sp1无效 这就是个v7.1 sp1的key_gen
lab2_VHDL
- VHDL数字系统设计和工程实践1，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice, one that contains principles, truth table and schematic, as well as VHDL source code.