资源列表
74_alarm_clock
- 基于vhdl闹钟设计的实例，可以设置重置以及清零-vhdl alarm
rs232
- FPGA与PC串口调试工具通信程序，包括收和发两个过程。-Program for communication between FPGA and the PC serial port debug tool ,including sending and receiving processes.
DE2_70_TV_PIP
- DE2的代码，主要涉及画中画的处理，用了独特的处理方式，值得借鉴。-The DE2 code, mainly related to the processing of the picture in picture, with a unique approach, it is worth learning from.
DE2_70_AUDIO
- DE2的音频处理，用了独特的方式，有一定的借鉴意义。-DE2 of audio processing
FPGA_Programming
- 介绍FPGA的基本结构、开发流程与Verilog HDL语言基础，并附有加法器、移位寄存器等代码的实现。-Introduce the basic structure of the FPGA development process, and Verilog HDL language foundation, along with the adder, shift register code.
Example1
- fifo verilog hdl along with test bench its hardware
Example1B
- verilog code with its test bench
Example2
- this one also verilog source code with its test bench
Example2B
- this one also verilog code with its test bench
ROM-based-sine-wave-generator-of-the-design-the-u
- Rom based Sine wave generator
Micro-SD
- 数字模组将各种扩展功能以统一的总线方式引出，再通过原系统的控制板，连接相应的外设接口，以实现对应的功能；-Digital module will be a variety of extensions to the unified bus lead, then through the system control panel, connecting the corresponding peripheral interface, in order to realize the correspondi
parallel-CRC-calculation-in-FPGAs-
- 给大家介绍关于crc校验原理和算法。并在fpga实现描述。-To introduce the crc check principle and algorithm。To achieve the descr iption in fpga