资源列表
DVD2_DFT_Project_Data[1]
- moore ckt source code
verilog-design-of-the-traffic-lights
- 基于verilog的交通灯程序，课程设计的时候绝对用得上-The text is about how to design the traffic lignt it is very useuful
testbench
- FPGA逻辑实验中，用VHDL语言实现IP核生成的实验。-FPGA logic experiment, with VHDL language implementation IP nuclear generated experiment.
async_transmitter
- RS232的FPGA code，利用Verilog實現傳輸的部分。
basic.program.vhdl
- example for basic program in vhdl
2
- 利用VHDL语言编程，产生一组PWM波，PWM波的频率为10kHz,占空比00—100 可调-VHDL programming, resulting in a set of PWM wave PWM wave frequency is 10kHz, and 00-100 duty cycle adjustable
jiandan28
- 基于VHDL的CPLD频率计，考虑节省资源的设计方案-Based on VHDL CPLD frequency meter, consider a resource-saving design
shouhuoji
- vhdl售货机源码,可用于课上作业，采用VHDL 编写，移植功能强-vhdl saler ,you can download it as a homework
cnt4
- 4-bit counter (VHDL project)
mimasuo
- 密码锁 支持修改密码 按任意键后 10秒未解锁则锁定-Locks to support modified password lock 10 seconds after any key to unlock
qpsk
- QKSK 调制 解调 调试成功 -QKSK modem debugging success
encrypt
- 完成汽车用HITAG2加密方式，用verilog完成-Completed the automotive HITAG2 encryption completed, with verilog