资源列表
EasyFPGA060_Routine_Adder
- EasyFPGA060 加法器实验及文档-EasyFPGA060 adder test and documentation
i2s_vmm
- inter IC Sound design with test bench written in Verification Methodology Manual.
verilogexample
- 里面包含verilog各种类别的器件的描述以及具体的实现方法-Which contains the verilog descr iption of various types of devices and the specific implementation method
verilog
- 一些基本器件的实现，包括选择器，计数器，移位寄存器，多位寄存器以及各种测试模块-The realization of some of the basic devices, including the selection, counters, shift registers, a number of registers and a variety of test modules
sellor
- 数字系统设计，用VHDL语言编程完成自动售票功能-Digital system design, VHDL programming language features to complete the ticket
5
- 基于FPGA的数字秒表的VHDL设计,论文,有主要程序-FPGA-based VHDL design digital stopwatch, paper, a major program
vme_sv
- voice modulation engine, a DSP processor with test bench written in SystemVerilog
Bibus
- bibus verilog example
Simply3verilogexample
- Sympli 3 verilog example
clock
- Real simply clock on verilog
VHDL-djdplj
- 基于VHDL语言的十进制等精度频率计的设计，采用VHDL语言，运用自顶向下的设计思想， 将系统按功能逐层分割的层次化设计方法，使用Quartus8.0开发环境，实现了频率计的设计。-VHDL language based on the decimal precision frequency meter, etc. The design, using VHDL language, the use of top-down design, the system is divided by func
djdplj
- 运用等精度测量原理,结合单片机技术设计了一种数字式频率计,由干采用了屏蔽驱动电路及数字均值滤波等技术措施,因而能在较宽的频率范围和幅度范围内对频率、周期、脉宽、占空比等参数进行测量并可通过调整闸门时间预置测量精度。-The use of other precision measuring principle in combination with single chip technology to design a digital frequency meter, shielded from t