资源列表
EasyFPGA060_Routine_Shifter
- EasyFPGA060 移位寄存器实验例程和文档-EasyFPGA060 shift register and document experimental routines
EasyFPGA060_Routine_Comparator
- EasyFPGA060 比较器实验例程和文档-EasyFPGA060 comparator test routines and documentation
EasyFPGA060_Routine_RAM
- EasyFPGA060 RAM实验例程与文档-EasyFPGA060 RAM test routines and documentation
VerilogHDLexample
- 可综合的VerilogHDL设计实例 ---简化的RISC CPU设计简介-VerilogHDL comprehensive design example can be simplified RISC CPU design--- Introduction---
Vhdl
- Very hardware descr iption language tutorial
SystemVerilog_3.1a
- System verilog manual 3.1
SystemVerilogforDesignsecondEdition
- ebook for SystemVerilog for Design second Edition
3
- 】文章介绍了用于体育比赛的数字秒表的VHDL 设计, 并基于FPGA 在MAXPLUS2 软件下, 采用ALTRA 公司FLEX10K 系列的EPF10K10LC84- 4 芯片进行了计算机仿真-】 This article introduces digital stopwatch for sports competition in the VHDL design and FPGA-based software in MAXPLUS2, using ALTRA company FLEX10K
arbiter_priority
- A priority arbiter design which will help some people out there. hope this will be useful for verification engineers
can2spec
- CAN Specification for people looking forward to design Verification IPs and design IPs
EasyFPGA060_Routine_Decoder
- EasyFPGA060 编码器实验及文档-EasyFPGA060 Encoder test and documentation
EasyFPGA060_Routine_SynFIFO
- EasyFPGA060 同步FIFO实验-EasyFPGA060 synchronous FIFO test