资源列表
ds18b20_verilgo
- 艾米电子的verilog HDL描述的DS18B20的程序-Amy verilog HDL descr iption of the procedures DS18B20
Sinusoidalsignalgenerator
- 正弦信号生成行为级描述，结构级描述全套，适合仿真-Sinusoidal signal generated behavioral descr iption, a full set of structural level descr iption for simulation
serial_communication
- 使用Xilinx公司的FPGA，采用Verilog HDL语言实现串口数据的发送与接收。-Using Xilinx' s FPGA, Verilog HDL language used to send and receive serial data.
jiancelvbo
- 滤波器加上功率检测的verilog语言，对于嵌入式研发人员有较大的帮助，由于能力有限，请多包涵-Filters with power detection verilog language for embedded developers have a greater help, as capacity is limited, like him indulgence
filteramp
- 该VHDL程序编写了各种滤波器和放大器，对于刚学VHDL的同学有极大的帮助-The VHDL programming a variety of filters and amplifiers, for students just learning VHDL great help
HowtousePerlinyourVerilogHDLDesignFlow
- use Perl in your Verilog HDL Design Flow,利用Perl语言方便管理Verilog HDL 代码。-How to use Perl in your Verilog HDL Design Flow
TIMER
- 介绍QuartusII 的TIMER的一些基本情况-Introduction QuartusII' s some basic information TIMER
LED-DISPLAY
- 在DE2板上 （nios II）实现LED的年月日，时分秒的显示。-Achieving LED s year, month, day, hour, minute, seconds display in the DE2 board (nios II).
FlashDriver
- 用VHDL实现NAND Flash 的I/O 读写操作-with VHDL programme realize NAND Flash I/O read & write
AX_Clock_Dithering_AN
- Frequency fine tuning and clock dithering using ACTEL FPGA devices.
sumador_divisor
- suma dos señ ales y las divide entre 2
UART
- UART receiver transmitter verlog code