资源列表
XLXH
- 完成序列为0111010011011010的序列生成器 2．用状态机设计实现串行序列11010的检测器 3. 若检测到符合要求的序列，则输出显示位为“1”，否则为“0” 4. 可对检测到的次数计数 -Complete sequence is 0111010011011010 sequence generator 2. State machine design using serial sequence of 11 010 detector 3. If the sequence i
subber
- 完成一位二进制全减器的设计，采用原理图输入法和文本输入法分别实现，分层设计，底层由半加器（也用原理图输入法）和逻辑门组成-Completion of a binary full subtracter design, the use of schematic and text input method input method were realized, hierarchical design, the bottom of the half adder (also used schematic
DAstate
- 状态机，用FPGA控制DA发送串行指令方案-State machine, with the FPGA to send the serial command control program of DA
canlender_clock
- 电子日历的设计源代码 verilog程序设计 通过仿真-The design of electronic calendar program design verilog source code simulation
ddr2_test
- 一个用Verilog写的DDR2的控制器（我们项目是在Altera的FPGA）成功仿真，并且使用到了项目中控制DDR2-A written using Verilog DDR2 controller (our project in Altera' s FPGA) successful simulation, and used to control the DDR2 in project
use_FPGA_control_VGA
- 实现了用fpga控制vga的输出，资料简单，但是具有代表性。-To achieve control using fpga vga output, the data is simple, but representative.
verilog_hjckzn
- Verilog 黄金参考指南是 Veri log 硬件描述语言及其语法 语义 合并以及将它应用到硬件设计的一个 简明的快速参考指南-Verilog Golden Reference Guide is Veri log hardware descr iption language and its syntax and semantics of merging hardware design to apply it to a concise Quick Reference Guide
FPGA_drive_VGA_test_verilog
- FPGA drive VGA test verilog
apple2fpga-0.1.tar
- cade in vhdl to implement fpga computer apple2 type
lcd3
- lcd display on windows
lcd2
- lcd display vhdl windows
Verilog_example_code
- 包含了很多简易的基础的程序，对于verilog入门很有益处的-Base contains a lot of simple procedures for entry is very beneficial for verilog