资源列表
dp_ram
- 双口RAM的设计，采用Verilog HDL语言编写。-Dual-port RAM design, using Verilog HDL language.
halfadder
- vhdl code for half adder using libero software
ram
- vhdl program for random access memory and sequence detector
trafficlight
- traffic light controller vhdl program
RS-232
- 串口通信模块Verilog代码及相关文档-Serial communication module Verilog code and related documentation
SDRAMcontroler
- SDRAM控制器，Verilog代码以及相关文档-SDRAM controller, Verilog code, and related documentation
i2c
- 该压缩包包含了i2c core设计需要的文献资料以及verilog编写实现i2c通信的源代码-The archive contains the i2c core design requires the preparation of literature and the verilog source code to achieve i2c communication
MIMO
- 介绍MINO系统在FPGA下如何开发，详细的介绍了过程！-MINO system introduced in the FPGA how to develop a detailed introduction to the process!
S6_VGA_change
- 1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序可以在VGA显示器上以800x600分辨率显示方波示例和字母示例 3。具体设计参考代码。 -1. Source file in src directory, QII Proj project files in the directory 2. Program can display in 800x600 resolution VGA display and square-wave sample letters
S7_PS2_RS232
- 本实验实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）； 并在数据接收区显示接收到的字符。 串口调试终端的设置：波特率115200，一个停止位，无校验位。 -The experimental realization of PS/2 interface and RS-232 data interface, PS/2 keyboard, press the button, you ca
count
- 设置一位控制位M，要求M=0：模23计数；M=1：模109计数；计数结果用两位静态数码管显示，显示BCD码； -Setting a control bit M, requires M = 0: mode 23 counts M = 1: model 109 counts counting results with the two of static digital display to show BCD code
Verilog
- 用verilog实现的电子日历程序,在Quartus II上编译通过-Implemented using verilog electronic calendar program, compiled by the Quartus II