资源列表
cun
- 通过fpga使总线上的数据存储到spi进行读写-Through the fpga to store data on the bus to read and write spi
VHDL_coding
- Powerpoint slides about VHDL coding which teaches in class, inculdes many lesson and also parctice.The ppt file is for learners who want to begin with VHDL.
pruebacont
- Param Counter Verilog
Logicos
- Is a Simple andOr, xor, sr circuit on Verilog and his testBench
myCounter_top
- A simple Counter code inculdes core of ICON VIO ILA, works on ISE 12.2 and chipscope to test the board.
ADPCMDecoder
- ADPCM decoder working on Xilinx ISE 12.2 code includes core ICON ILA VIO test on chipscope
ADPCMEncoder
- ADPCM encoder with ICON, VIO, ILA, working on Xilinx ISE and chipscope.
Chipscope_example
- A easy simple for Xilinx Chipscope Pro, the example shows how to insert cores of VIO, ILA from core generator and verilog code.
writeandreadSRAM
- 最近操作了诸如UT62256,GM76C256,IS61LV5128 等SRAM 芯片，基本上他们 的时序操作大同小异，在这里总结一些它们共性的东西，也提一些简单的快速操 作SRAM 的技巧。-Recent operations such as UT62256, GM76C256, IS61LV5128 other SRAM chips, the timing of their operation is basically similar, and here summarize some
factorial
- verilog code for factorial algorithm
asynchro2bitupdownneg
- this a verilog code for asynchronous 2 bit up down counter with negative edge triggered.-this is a verilog code for asynchronous 2 bit up down counter with negative edge triggered.
mod6asynchro
- this is a code for mod-6 asynchronous counter in verilog.