资源列表
Syn_FIFO
- 基于Actel公司的开发平台，verilog实现同步fifo设计-Double port ROM verilog realization, based on the development of the Actel development platform based on Actel company development platform, verilog simultaneous fifo design
DE2_70_TV_sobel.7
- DE2_70_TV與DE2_70_D5M_LTM的架構非常類似，都是以SDRAM當做frame buffer，所以若要加上演算法，基本上也是放在SDRAM之前做前處理，或者放在SDRAM之後做後處理。-The architecture DE2_70_TV and DE2_70_D5M_LTM very similar, as a frame buffer, so coupled with the algorithm to, basically on the SDRAM before doing
Static-PLL
- 基于Actel开发平台的静态锁相环设计，verilog实现-Actel development platform based on the static PLL design, verilog realized
even_divider
- 第一次上传文件，已通过仿真测试，可以实现任意的偶数倍分频-Achieve any even frequency divid
slau144i
- 数字频率计可以实现0.1---50khz的频率测试，小于1000时采用测周法，大于1000时自动转为计数法，最大误差小于千分之一，基本保持在万分之一之内。试验板采用12Mhz晶振，74164静态数码管显示，CD4051信号调理输入TTL方波信号-MPS430Visual C++, cd4051 ProgrammersHeaven
63bit1amount
- 求63位二进制数前导1个数Verilog-Solution for 63bit-FL1. Writen with Verilog.
Verilog-digital-design-and-synthesis
- 学习verilogHDL语言的经典之作！-a guide to digital design and synthesis (second edition)
Example-b4-1
- 1. 定制一个双端口RAM，DualPortRAM 2. 在顶层工程中实例化这个RAM 3. 实现这个工程，在Quartus II仿真器中做门级仿真 4. 在ModelSim中对这个工程进行RTL级仿真 -Customize a dual port RAM, DualPortRAM On the top floor of the RAM engineering instantiation To realize the project, in Quartus II simu
ALU
- ALU 与ALU控制器 实验 VHDL Verilog 语言设计-ALU VHDL Verilog
zhankongbi
- 能对输入的方波信号进行占空比测试，在两位数码管上显示出来-Can the input of square wave signal than empty testing, in two digital tube test results show that will come out
FPGAled
- 通过状态机对输出状态进行切换，产生不同的效果-Through the state machine to switch the output state, produce different effect
logic
- 学习FPGA常用的一些门电路，各种门电路，D触发器-Some of the commonly used learning FPGA implication