资源列表
vhdlsourcecode
- some vhdl sourcecode,just for freshmen to read
XC3S400
- XC3S400 minimum system with XCF02S platform flash very useful
EP1C3_12_9_DDS
- 直接数字式频率合成器(DDS)设计实验(电子设计竞赛赛题) 其它详细资料说明请参考 http://www.kx-soc.com-direct digital frequency synthesis (DDS) experimental design (Electronic Design Contest tournament title) said other details Please refer to prescribed http://www.kx-soc.com
Verilog_juzhenjianpan
- 采用Verilog编写的4x4矩阵键盘的程序。该程序经过验证可行。-Implementation of 4x4 matrix keyboard Verilog language. After verification, the feasible.
Nios2_SCH
- Nios2_SCH 原理图，可以参考设计-Nios2_SCH schematic, you can reference design
cpu
- 基于VHDL的单周期cpu开发，网上找的-cpu design
2048Mb_ddr3
- 美光DDR3存储器模型，用verilog语言编写，通用模型-DDR3 MEMORY
Axi_mux
- The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the lib
lab2_VHDL
- 这是基于VHDL的编程练习，适合于初学者学习VHDL编程，通俗易懂，简明扼要。
zhenxianfashengqi
- 调用SIN输出四路相位不同正弦波发生器，输出信号幅值是0~A-Four different phases called SIN output sine wave generator, the output signal amplitude is 0 ~ ACC
FPGA0
- SRAM读写时序，先读入一串数据，然后再实现输出-SRAM write and read
10-sequence-detector
- 本系统采用实验箱的48MHz时钟作为输入时钟，将其分频得到计数器计数频率和序列检测器检测序列频率-The system uses a 48MHz clock experimental box as the input clock, to get the counter frequency divider and serial sequence frequency detector