资源列表
jcq
- vhdl,序列信号检测模块，此模块检测1110010，可改为任意序列，输出电位为1为检测出，否则为0-vhdl, sequence of signal detection module, this module testing 1.11001 million, can be changed to an arbitrary sequence, the output potential of an as detected, otherwise 0
jifenqi
- 基于vhdl的智力抢答器的程序设计，功能包括抢答 积分 减分 亮灯 等-Responder based on intelligence vhdl program design features include the answer in points by sub-light, etc.
4bitcomp
- I try 4-bit comparator here in VHDL
uart
- 一种串行uart接口的实现，可支持对种通信速率，modlesim仿真-Realizing serial uart interface, which can support a variety of communication speed, modlesim simulation
uart_v11
- uart串口的vhdl语言程序。本人调试过 ，非常好用
digitalclock
- 数字秒表，有六进制、十进制，顶层文件。很大方哈萨克活动时间啊客户-digitalclock
ADC08099
- 利用VHDL进行嵌入式设计编程，ADC08099模数转换芯片接口程序设计-VHDL programming of embedded design ADC08099 analog-to-digital conversion chip interface programming.
乘法器
- 乘法器的源代码，以及其测试文件，testbench，是word的形式
VHDL_SPI
- 使用的程序，大家可以借鉴，对FPGA初学者有用(Use of the program, you can learn from the FPGA beginners useful.)
Basys-3-GPIO-2016.4-1
- Test for GPIO for basys3, made by digilent
altera_avalon_pwm
- 基于nios2的PWM模块设计，兼容avalon总线结构(PWM module design based on nios2, compatible with Avalon bus structure)
water_led_design
- 一个项目吧，但是结构很完整，基本上都是必须的部分了，虽说只是流水灯-A project, but the structure is complete and basically essential part, although only light water