资源列表
cheb_s
- 用以滤除直流工频干扰的四阶切比雪夫高通滤波器传递函数。-four stage Chebyshev high-pass filter transfer function which is Used to filter out the DC frequency interference.
paobiao
- 一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
sweet16
- Sweet16 VHDL soft-core processor
DDC.rar
- verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用，好用。,Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.
cic
- 无线通信中的DDS原理，讲解了FPGA实现数字频率合成器-Wireless communication in the DDS principle, to explain the FPGA to achieve digital frequency synthesizer
Uart2
- uart的VHDL源代码，包括intface.VHD UART_RX_TAB.VHD UART_INT_TB.VHD等-uart VHDL source code, including intface.VHD UART_RX_TAB.VHD UART_INT_TB. Volume etc.
87361001Uart2
- VHDL语言编写的UART串口通讯,2400Hz的波特率时钟-VHDL language UART serial communication, 2400Hz clock of baud rate
mux1_4
- 双4选1的数据选择器 输入信号：使用按键1、2、3、4 选择信号：使用按键7、8-Dual 4-to-1 data selector input signal: use keys 1,2,3,4 select signal: use keys 7-8
vhdl5
- VHDL Language Reference courses part5 last
daima
- 32bits提前进位加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits advance carry adder verilog language, xilinx chip run through
Twofish
- 基于FPGA的Twofish加解密系统，通过FPGA验证代码为Verilog,开发板为DE2-115-Twofish encryption and decryption system based on FPGA, through the FPGA verification code for the Verilog development board, DE2-115
SPDIF-interface-IP-core
- SPDIF数字音频接口的的程序，已写成通用IP核形式。-The program SPDIF digital audio interface has been written in the form of common IP core.