资源列表
PLL
- 基于EP2C8的锁相环倍频文件 原来时钟为25Mhz 倍频为100Mhz-File the original clock of the EP2C8 the phase locked loop frequency multiplier 25Mhz for 100Mhz
an490
- Altera官方网站提供的MAXII系列CPLD做电平转换的应用文档，非常实用的。-Official website of the MAXII Altera CPLD family to do the application-level document conversion, very practical.
RS232
- RS232的一个verilog程序。
rs232
- fpga的串口读写程序，经硬件测试成功，波特率9600.可以改变分频值适应不同的时钟和波特率-fpga serial read and write procedures, by the hardware to test the success of 9600 baud rate. frequency value can be changed to adapt to a different clock and baud rate
CVI-SCOPE
- 用开发板内核来实现FPGA开发板通过USB端口通信程序-Development board with FPGA development board to implement the kernel through the USB port communication program
pll
- 用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
edge
- 图像处理中边缘检测的VHDL源代码,所用的算法是garbor变换-Image processing edge detection of VHDL source code, the algorithms used are garbor transform
image_ver_main
- The design of multi level sensor is mostly based on FSM controller-The design of multi level sensor is mostly based on FSM controller
ep2c35
- Cyclone 2 Altera PDF
control_tube
- 定义LX6系列针脚，并实现计时器，最大可以数到60min，局限于只有四个tube(Define the LX6 series pin and implement the timer,)
key_led
- led灯按键控制 VerilogHDL 始于FPGA入门学习-led control VerilogHDL
mux4_with_en
- 带有使能端的4输入数据选择器，S0, S1, S2, C0, C1为输入，C1，C2为使能输入，P, Q, R, T为输出，c1c2=00时输出全为0，c1c2=01时输出全为1，c1c2=10时数据选择，c1c2=11时输出是c1c2=10时的反。-4 with Enable input data selector, S0, S1, S2, C0, C1 as input, C1, C2 an enable input, P, Q, R, T as an output, c1c2 = 00 a