资源列表
zhong
- 基于CPLD的多功能数字钟编程，具有闹钟，整点报时，倒计时，日历等功能-CPLD-based multi-functional digital clock programming, alarm, hourly chime, countdown, calendar and other functions
RS232
- PLD 竞赛中 alter de0开发板 自带的R232 串口驱动程序 用于高速传输-Competition alter de0 PLD development board comes with R232 serial port driver for high-speed transmission
adc
- 实现模数转换功能,采样频率为时钟频率的36分之1，可以双路同时采样，并且串行输出，输出数据14位有符号数。-The analog-to-digital conversion, the sampling frequency is 1/36 of the clock frequency, can be dual simultaneous sampling, as well as serial output, the output data 14 of the number of symbols.
ccd
- Verilog编写的夏普ccd涉嫌头工程。可在tft上显示采集的视频-failed to translate
Sum
- 4位二进制数加法器，利用拨码开关作为输入，7段数码管作为输出。-4 binary adder, using DIP switches as input, 7-segment LED as output
Timingbook
- Timing design for FPGA. Good document for advance learner of FPGA.
ALU32
- 32 bit ALU RTL Code using VHDL
VHDLadderdoc
- 为了减轻大家负担，在次把带进位输入的8位加法计数器上传，希望能出分；力-In order to alleviate the burden on everyone, in time to enter into an 8-bit adder counter From the hope of a points force
cy7c68013fpga_code
- cy7c68013的fpga配置代码，verilog语法-cy7c68013 the fpga configuration code, verilog syntax
AlteraFPGACycloneDemo2DigitalCounter
- Example shows how to program Altera FPGA Cyclone Family using VHDL Programming Language
uart
- 串口通信程序，硬件描述语言VHDL，代码简洁，功能完善-Serial communication program, hardware descr iption language VHDL, the code simple and functional. . .
paomadeng
- 基于VHDL语言的4X4键盘 通过仿真 可用-keyboard