资源列表
eetop.cn_1
- nor flash 控制器 硬件描述语言描述-nor flash controler
MIPS_shift_8bits
- ARM架构下的8位桶形移位器的verilog源码-8 barrel shifter ARM architecture of verilog source
communication-controller
- 该异步通信控制器主要采用状态机设计完成。包括异步发送端和异步接收端。可异步进行信号的收发-The asynchronous communication controller mainly USES the state machine design completed. Including asynchronous the sender and receiver asynchronous. Can signal to send and receive the asynchronous
sequentialcircuits
- vhdl编程国外教程，英文版，集成电路时序逻辑编写-vhdl programming tutorial abroad, English, integrated circuits, sequential logic to prepare
altera_up_avalon_character_lcd
- LCD例程 altera官方Verilog代码 详尽简单实用-LCD routines altera official Verilog code is simple and practical details
GL830
- USB2.0转sata-GL830 资料-USB2.0 to sata-GL830
XSA-PS2KBD
- ps2 keyboard vhdl project
vga
- QUARTUSII 环境 内容为整个工程 ，可以直接用 VHDL 实现VGA通讯-QUARTUSII environmental elements for the entire project, you can directly communicate with the VHDL implementation of VGA
12
- 基于VHDL的四位出发起的设计，经过仿真和验证，并在FPGA上实现-VHDL AND DIVDER DESIGN
s_clock
- 时钟，从一小时开始，也可实现倒计时，使用了8个数码管-Clock, an hour from the start, but also realize the countdown, the use of the 8 digital tube
Verilog HDL Practice
- FPGA Verilog HDL程序设计练习进阶，实用的FPGA学习资料。(Practicing of FPGA Verilog HDLprogramming)
initial_lib
- Vivado的初始库文件，内含74LS系列IP模块和XUP系列模块(The initial library file of Vivado contains 74LS series IP module and XUP series module.)