资源列表
51CTODATALAYERPRODUCE
- 华为对于数据链路协议的介绍，对于初学者或有意了解华为的人，有很大的帮助。-Huawei for the introduction of data link protocol, a great help for beginners or people interested in understanding the Huawei.
FPGA-CPLD_DesignTool(5-6)
- FPGA-CPLD_DesignTool(example5-6),需要的朋友可以下载-FPGA-CPLD_DesignTool (example5-6), a friend in need can be downloaded
gpsfpga
- gps design using fpga project thesis very useful
zhl
- 设计一个跑马灯控制器，能够根据外部的拨码开关进行速度控制。在速度控制的基础上，根据外部开关变换跑马灯显示方式。-Design a Marquee controller speed can be controlled according to the external DIP switches. On the basis of the speed control, according to the display mode change Marquee external switch.
GPS-FPGA源代码
- 这个是基于ALTERA-FPGA的GPS程序实例，
uart
- QUARTUSII 环境 内容为整个工程 ，可以直接用 VHDL 实现UART通讯-QUARTUSII environmental elements for the entire project, you can directly communicate with the VHDL implementation of UART
4_2
- 4位二进制加法计数器,实现简单的加法功能,最高支持4位,用二进制形式计算.-Counter 4-bit binary addition, addition of simple features, up to 4, with binary calculations.
application-in-card-and-servo-drive
- AB相编码器解码接口_PWM输出SOPC方案及其在运动控制卡和伺服驱动器中的应用-AB phase encoder decoder interface _PWM output SOPC program and its application in motion control card and servo drive
ad0809
- adc0809 转换，verilog代码-adc0809 conversion, verilog code
first-follow
- first follow集合生成器 我晕。还嫌我说的少-first bu jiushi shang chuan dong xi ma
Lvds_lattice
- 这是基于lattice fpga 芯片的 ttl 24bits（rgb888）模块。简单易懂，修改输出分辨率只需要修改几行宏定义。整个工程文件在diamond2.0版本上编译运行。-This is based on ttl 24bits lattice fpga chip (rgb888) module. Easy to understand and modify the output resolution is only need to change a few lines of macro
digitalclk
- 用maxplus编写的时钟程序。包括天、时、分、秒-make use of language of maxplus to make a clock.include day,hour,minute,second