资源列表
usb11_latest.tar
- its all about implementation of usb 1.1 core
Fifo
- 在quartus2中实现FIFO并仿真通过-FIFO is implemented in quartus2 and simulation by
Chipscope_example
- A easy simple for Xilinx Chipscope Pro, the example shows how to insert cores of VIO, ILA from core generator and verilog code.
sdram_ip_doc_preliminary
- 关于的SDRAM ip核相关资料汇总，SDRAM,SDRAM-On the SDRAM ip summary of nuclear-related materials, SDRAM, SDRAM
klt1
- klt算法的fpga实现，使用altera公司的开发环境。-the klt algorithm of the fpga implementation, altera company s development environment.
LVDS_8BIT
- verilog 写的LCD 画面显示程序，优化后速度很高。-lcd display driving code of verilog,high speed support.
DE2_70_TV_PIP
- DE2的代码，主要涉及画中画的处理，用了独特的处理方式，值得借鉴。-The DE2 code, mainly related to the processing of the picture in picture, with a unique approach, it is worth learning from.
DCM
- ISE实现DCM组建例化，得到3倍频时钟-ISE to achieve established cases of DCM, received 3 octave clock
FHT_example
- 面积和速度的互换是FPGA/CPLD设计的一个重要思想。乒乓操作、串并转换-The balance between area and speed is a important idea in the design of FPGA/CPLD. Ping-pong operation、the conversion between series and parellel
dpll1600e
- 数字锁相环的设计，包括鉴相器，环路滤波器，spi口输出，分频器的源代码-Digital phase-locked loop design source code, including the phase detector, loop filter, spi port output divider
spi_iic
- spi_iic的接口代码，利用lattice的FPGA验证过，很经典的收藏电路-spi_iic interface code, the use of lattice FPGA verification, the classic collection of circuit