资源列表
AD_sample_100Mhz
- verilog写的四进制加法器 verilog写的四进制加法器-verilog
S9_LED_RUN
- 用Verilog语言编写的用于驱动led灯-this is a code for drive leds in verilog
FIRFILTER
- 16阶数字滤波器 VHDL语言编写 已经全部编译成功-16-order digital filter VHDL language have all been compiled successfully
spartan_ethernet
- Ethernet FPGA for spartan 3e startet kit, 1,10,1000 Mbps
8X8LED
- 基于 qusrtus II上的 MAX ii 系列 FPGA上的数码管动态显示VHDL程序-Based on the MAX ii qusrtus II series FPGA, VHDL dynamic display of digital control program
UART
- 串口测试程序 基于FPGA的MAX II系列的VHDL源程序端口已经设置好-Serial port test program is based on the MAX II family of FPGA VHDL source port has been set up
lcd_1602_v
- 基于FPGA的1602显示程序，端口管脚已经设置好，拱大家学习-FPGA-based display program 1602, the port pin has been set up, we learn arch
CPU
- VHDL16位cpu，能实现加减法移动等指令-vhdl 16 cpu,include add,sub,move and so on.
VGA2
- 基于FPGA的VGA显示程序 测试过的，是VHDL源码-FPGA-based VGA display program tested, is VHDL source
filter1
- 题为基于CSD编码的FIR数字滤波器设计.该滤波器具有线性相位,系数减半.采用VHDL语言编写.是我们EDA课程的作业,得了优.希望对大家有用-Entitled based on CSD code FIR digital filter design. That the filters have linear phase, coefficient half. Using VHDL language. Is the EDA program operations, got excellent. Hop
4_bits_MCU_AM2901
- 4位MCU AM2901的完整VHDL程序-4-bit MCU AM2901 complete VHDL program
VHDLexamples
- 这里面有很多的vhdl的编程的源代码，文件是全英文的，例子丰富-That there are a lot of vhdl programming source code, documentation is in English, and examples of rich