资源列表
lab1-lab3
- XILINX EDK中三个简单的实例！有PDF详细说明-XILINX EDK in three simple examples! A PDF details
flf
- 乘法器的计算方法和程序，适合新手学习语法，直接的代码-mulcon
vhdl
- 这是基于VHDL设计的抢答器 通过抢答者的指示灯显示、数码显示和警示显示等手段指示出第一抢答者-This is based on VHDL design Responder Responder' s light show through a digital display and warning display means of the First Responder who directed
shuzitiaozhijietiaoqi
- 数字调制解调器 数字调制解调器 -Digital Modem
ref-ddr-sdram-verilog
- ddr_sdram开发参考verilog建模-ddr_sdram with verilog
ref-sdr-sdram-verilog
- sdram的verilog 建模参考设计，希望有所帮助-sdram and verilog implent
can
- can总线的verilog设计与实现，很好的资料哦-the implention of can bus with verilog
stc
- stc设计与实现，也即时间增益放大的设计，工程中有很多用处。-the implention of stc
44_reg_counter
- 用VHDL写的计数器程序例子，
DigitalWatch
- Digital watch write in Verilog HDL language simulate the real clock in Atera DE2 development board
rs232
- uart rs232 receiver and transmiter
qiangdaqi
- 六路数字式抢答器的主要仿真程序，容纳6组参赛的数字式抢答器，当第一个人按下抢答按钮时，其他组的按钮不起作用。当主持人按下“复位”按钮，所有组的按键才可用。-Six Road, a major digital answering device simulation program, up to 6 groups participating in the digital answering device, when the first one to answer in the button pres