资源列表
fpga_chufaqi
- 基于fpga的32位除法器的设计，开发环境vhdl-Fpga-based 32-bit divider design, development environment vhdl
lcd
- 128*64点阵液晶显示控制器时钟模块，quartus II 运行-128* 64 dot matrix LCD controller clock module, quartus II run
krtlcd
- 基于FPGA的液晶显示驱动知识研究，可在quartus II环境下运行-FPGA-based knowledge of liquid crystal display driver can be run in quartus II environment
GP_REG_3R1W_64X64
- 64X64 bits SRAM 模型 64 X64 bits SRAM 模型-SRAM Models
gen_ecc
- ecc generator Error Correction Coding -ecc generator Error Correction Coding
EDAdesigntechnologystopwatch
- EDA技术之_秒表的设计 （1）有使能、暂停、继续秒表计数功能 （2）带有异步复位功能 -EDA technology _ stopwatch design (1) enable, pause, resume, stopwatch counting function (2) with asynchronous reset
FPGAPS2interface
- FPGA控制的PS/2接口 内容是基于状态机的FPGA控制的PS/2接口 大家看看 不好的提出建议-FPGA-PS2-interface
vhdl
- 3分频 器，LED分位译码电路，交通控制器，序列检测器-four programs based on vhdl
CLOCK3
- 时钟与报警器源程序，功能强大，资源少。操作简便-Clock and alarm source, powerful, less resources. Simple
qj
- 全加器。使用Vhdl语言实现数字电路全加器功能，算法比较简单，供初学者参考。-Full adder. Digital circuits using Vhdl language full adder function, the algorithm is relatively simple for advanced users.
SINGT
- 简单的正弦信号发生器。利用lpm功能模块设计。-Simple sinusoidal signal generator. Design of functional modules using lpm.