资源列表
Altera-EP2C8Q-Nios-Example
- Altera EP2C8Q Nios例程-Altera EP2C8Q Nios Examples
NIOSII_TFT
- 基于FPGA的NIOSII_TFT做的做的正弦波很连贯的显示在液晶屏上面，FPGA主要做信号的产生，而NIOSII主要是驱动液晶画活出波形！-FPGA-based NIOSII_TFT do make a very coherent sine wave displayed on the LCD screen above, FPGA mainly to do signal generation, while NIOSII mainly driven liquid crystal painting
TFT_zhengxianbolianguanxainshi
- 基于触摸液晶的正弦波显示，相当于示波器的屏幕，很使用的源代码，希望对各位有用！-LCD display touch-based sine wave, the equivalent of the oscilloscope screen, is the use of the source code, in the hope that useful!
addfinal
- 37位的29个数加法器。用于位数较多的多个数相加。-37 the number of the adder 29. Median more for multiple numbers together.
dff9
- 9位的同步D触发器，带清零功能，可用于数字电路设计-9 synchronous D flip-flop with clear function
freq_4
- 4分频时钟，同步，带清零功能。可用于时钟分频设计-4 divided clock, synchronization, with clear function. Can be used for clock divider design
multt
- 该程序实现了一个16*16的乘法器，可以用作设计乘法器参考-The program implements a 16* 16 multiplier, multiplier design can be used as reference
16_QAM
- 用verilog 语言编译16QAM调制-a great complied code of 16QAM modulation for OFDM
data_scramble
- 用verilog 语言编译数字通信中的符号扰码，预防长1或长0的出现-a great complied code of data sramble for OFDM
CP_adder
- 用verilog 语言实现数字通信中最先进的技术之一中的OFDM技术中的添加循环前缀，可以减少码间干扰，并实现符号同步-a great complied code of cyclic prefix for OFDM which is good for intersymbol interference and inter channel interference
Freq_Count_Test-8.15
- Verlag代码，频率计，计算输入触发信号的频率，频率=工作时钟/计数结果。-Verlag code, frequency meter, calculate the input trigger signal frequency, frequency = operating clock/count the results.
LAB2
- 一步 学ZedBoard & Zynq-STEP BY STEP STUDY ZedBoard & Zynq