资源列表
CodedLOCK
- 基于FPGA的电子密码锁设计与实现，语言是VHDL语言，有注释-FPGA-based design and implementation of electronic locks, language is VHDL language, annotated
ManchesterCode
- VHDL编写的曼彻斯特编码程序，已验证通过，文件为完整的工程-VHDL, Manchester coding process has been verified through the file for the complete project
Embedded-Systems-Lab-2
- Configure your altera fpga and get features explored
generate-coordinates
- 使用VHDL编写语言，巧妙的利用计数器和循环输出一个坐标系，由于VHDL出现负数比较麻烦，全部由正数代替，输出一个原点在中心，半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。-Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive numb
EDA-experimental-guide-book
- 利用QUARTUS II 8.1软件进行简单的EDA设计。该实验指导书原理阐述清楚，内容详尽，实验过程描述清楚，每一个实验步骤都有具体的截图。该实验指导书包括四个基本实验：实验1 QUARTUS II 8.1软件的使用；实验2 图形法设计24进制计数器；实验3 60进制计数器；实验4 简易数字钟。-Use QUARTUS II 8.1 software for simple EDA design. The experiment instructions Rationale clear, deta
Desktop
- 频率检测，verilog hdl,单片机用C8051F120外部中断0。测量范围2Hz到9MHz-Frequency detection, verilog hdl, C8051F120 microcontroller with external interrupt 0. Measuring range 2Hz to 9MHz
quartus-II-shuzizhong
- 数字钟的设计 包括电路图连接实现 可以加深对数字电路的理解-The design of digital clock including circuit diagram to connect implementation can deepen the understanding of the digital circuit
PLJ-XIANSHI
- 自制频率计，可以设置频率分辨率以及测频范围，基于altera FPGA-Homemade frequency meter, you can set the frequency resolution and frequency measuring range, based on altera FPGA
IIC-fpga-verilog
- 基于fpga的IIC设计，verilog-IIC fpga-based design, verilog
AVR-CORE
- 基于fpga的avr 软核 vhdl语言-Fpga-based soft-core vhdl language avr
kmp_matching
- 基于fpga的字符查找KMP算法，verilog语言-Fpga-based character lookup KMP algorithm, verilog language
rgb2ycrcb
- 基于fpga的RGB转YcRcB源程序，verilog语言-Fpga-based RGB to YcRcB source, verilog language