资源列表
lshifter
- 有时为了处理数据，需要将寄存器中的各位数据在移位控制信号作用下，依次向高位或向低位移动1位成为移位寄存器-Sometimes in order to process the data, you need to register in the role of data in the shift control signals, the order of low to high or to move one into the shift register
Xil3SD1800A_MIG
- 基于xc3sd1800afg676的开发板的DDR2的控制器的IPCORE，提供完整的代码和UCF。系统时钟频率为125Mhz。-The development board based on xc3sd1800afg676 DDR2 controller of IPCORE, provide a complete code and UCF. System clock frequency of 125Mhz.
mm1
- 基于随机数组中的最大值与最小值的选择器，可自由设定输出时钟和数组大小-Maximum and Minimum Value Selector
SpWIF
- spacewire 总线收发接口源代码，VHDL，适用于Xilinx，测试FPGA：XC3S1000FTG256-4C-spacewire bus transceiver interface, the source code, VHDL, applicable to Xilinx, testing FPGA: XC3S1000FTG256-4C
fsk_modulation
- 实现FSK调制功能，改变输入波形就可以有不同的输出-Achieve FSK modulation capabilities, to change the input waveform can have different output
fsk_demodulation
- FSK的解调过程，及仿真图形，改变输入可以得到不同的输出结果-FSK demodulation process, and simulation graphics, change the input can have different output
uart2
- a small uart implementation with Verilog
cpldtoPCvhdlcoding
- CPLD与PC机通讯的VHDL代码，实用性强。-CPLD and VHDL code PC, communications,
rs232
- RS232的串口控制器，本程序中的每个小模块都有与之对应的testbench，模块清晰，实现结构简单。很适合Verilog编程初学者来练习！-RS232 serial port controller, the program has a small module for each corresponding testbench, module definition, to achieve simple structure. Verilog programming is suitable for
NETFPGA_Documentation_self-extracting_package
- netfpga的相关文档以及其开源的一些工程和说明，这些资料不是很好找，现在收集齐了，分享给大家！-netfpga the documentation and some of its open source projects and instructions, such information is not easy to find, now collected together all the share to everyone!
QuartusII9.0crack
- quartus 2 v.9.0 program
lv7
- 该处理器的指令系统包括10条指令，分别是 （1）非访存指令 加法指令 ADD Ri,Rj(Ri+Rj->Ri) 减法指令 SUB Ri,Rj(Ri-Rj->Ri) 与指令 AND Ri,Rj(Ri and Rj->Ri) 或指令 OR Ri,Rj(Ri or Rj->Ri) 寄存器传送指 MOV Ri,Rj(Rj->Ri) 立即数传送指令 MVI Ri,X(X->Ri) （2）访存指令 存数指令 STA Ri,X(Ri-&g