资源列表
digital_frequency
- 用verilog实现数字频率计的设计，具有自动换挡功能，采用t法和m法设计，低频显示周期。量程为0.5~10Mhz。开发环境为quartus-This is a method of designing a digital frequency-measuring device. It can measure frequency ranging from 0.5Hz to 10MHz. It is developed in the program of Quartus.
fenpinpi
- quartusii软件仿真实验代码 分频器-quartusii software simulation code divider
jiafaqi
- quartusii软件仿真实验代码 十进制加法计数器-quartusii software simulation code decimal addition counter
miaobiao
- quartusii软件仿真实验代码 秒表 24小时计时-quartusii software simulation code stopwatch 24 hour time
8051_latest.tar
- VHDL/VERILOG FOR 8051 Core
can_latest.tar
- VHDL/VERILOG FOR CAN BUS Core
i2cslave_latest.tar
- VHDL/VERILOG FOR I2C Core
GPS
- 基于fpga的gps实现。代码完全可用 基于fpga的gps实现。代码完全可用-Fpga implementation based on the gps. Code fully available
key
- 4*4键盘扫描VHDL程序，程序中有产生键值，值得参考-heguo
verilog
- 北航夏宇闻verilog讲稿ppt语法入门-Wen Yu Xia Beihang verilog scr ipt syntax entry ppt
RW_flash_con
- FLASH-RW,完成FLASH的读写操作 FLASH-RW,完成FLASH的读写操作-FLASH-RW,完成FLASH的读写操作
Document
- vhdl code for 5509a evm