资源列表
0-8anjian
- 用FPGA实现的按键程序，9个按键显示数字0~8，已在quartus里面成功编译并用FPGA板验证过-failed to translate
liushuideng
- verilog HDL程序，功能：点亮LED灯，并实现右移的流水效果，已在FPGA板上验证过。-failed to translate
anjian-shumaguan-liushuideng
- verilog HDL语言，功能：按键控制，数码管显示多个状态，同时显示动态流水灯-failed to translate
liushui
- 用verilog编写的简易流水灯，里面包含分频器、选择器等，简单易懂。-failed to translate
3-8YIMAQI
- 基于fpga用verilog的3-8译码器，代码简单明了，适合初学者理解。-failed to translate
24xiaoshijishuqi
- 用verilog编写的24小时计数器，可以用作电子时钟，简单易懂。-Written in verilog 24 hour counter, which can be used as electronic clock, easy to understand.
JKchufaqi
- 基于FPGA的JK触发器，用verilog写的，简单明了，适合初学者。-JK flip-flop based on FPGA, written in verilog, clear and simple, suitable for beginners.
BCD_adder
- 基于FPGA的二进制加法器，简单易懂，适合初学者理解和接受。-Binary adder based on FPGA, simple, suitable for beginners to understand and accept it.
12864hanzixianshi
- 基于FPGA 的12864液晶显示汉字，用verilog编写的。-12864 liquid crystal display Chinese characters based on FPGA, written in verilog.
taxicounter
- 基于CPLD的出租车计价器，采用vhdl语言开发，能模拟实现出租车计价器的功能-Taxi meter based on CPLD, using VHDL language development, can realize the taxi meter simulation functions
ser
- FPGA的串并转换器。包括Verilog源码和时序仿真波形。-FPGA serial-parallel converter. Including the Verilog source code and simulation waveform.
mode3by3_generate_module
- 用verilog编写的3x3模块！用于图像处理算法中的中值滤波和边缘检测等等!-failed to translate