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资源列表
simple_spi_latest.tar
- A code a motorola compliant spi
ddc
- 信号处理前端 数字下变频 多相结构滤波 包含fir滤波器设计 非核- polyphase filter fir filter design DDC
sine-wave
- spartan-3an sine wave 波形通过dac显示 可改变sweep rate -spartan-3an sine wave based on VHDL
uart
- 利用verilog实现与uart的通信，uart接口-uart interface realize
data_convert
- 二进制码变换设计，完整的设计工程文件在data_convert文件夹下-Binary code conversion design, complete design engineering files in data_convert file folder
counter
- 四位计数器设计，完整的设计工程文件在counter文件夹下-Binary code conversion design, complete design engineering files in data_convert file folder...
multiplier_ip
- 基于IP核的乘法器设计，完整的设计工程文件在multiplier_ip文件夹下-IP-based core multiplier design, complete design engineering file multiplier_ip file folder
Verilog-coding-style-in-asic-design
- 该文档描述了ASIC芯片设计的verilog编程规范，这对芯片的正常流片极重要。-This document describes the verilog coding style in asic design.
asyn_fifo_bk
- 该verilog代码位手动编写的异步fifo。-This code is manually generated asychronous fifo.
multiply_shift_add
- 基于移位相加运算的乘法器设计，完整的设计工程文件在multiply_shift_add文件夹下-Multiplier design based on shift and add operations, complete design engineering file multiply_shift_add file folder
divider
- 基于移位相减运算的除法器设计，完整的设计工程文件在divider文件夹下-Based on the shift subtraction divider design, complete design project file divider file folder
cmosmt9m001_model
- 该verilog程序是型号为mt9m001的cmos图像传感器的仿真模型，能够输出频率为30Hz不同分辨率的图像。-This code is the simulation model of mt9m001 cmos sensor,it can output 30Hz and different resolution figure.