资源列表
canbus
- 此例参照SJA1000CAN通信控制器，通过CAN总线控制器完成CAN总线的通信协议。所传文件为CAN总线的VERILOG代码。-This reference SJA1000CAN communication controller, to complete the communication protocol of CAN bus through the CAN bus controller. The transfer document for the CAN bus VERILOG code.
frenq
- 用于等精度频率计测量程序,可下载至FPGA,或CPLD芯片中-Used for other precision frequency measurement procedures
vga
- 此例程为基于FPGAVGA/LCD显示控制的实例，用Verilog语言实现。代码中有详细注释。并有相应的仿真代码，可以验证其功能完整性。-This routine for the FPGAVGA/LCD display control based on examples, using Verilog language. The code has detailed notes. And a simulation code corresponding, can verify its function
VHDL-Snake-Game-simplify
- Vhdl-Snake game-Vhdl-Snake game........
9999counter
- 用Verilog编写的9999计数器，实现0-9999计数，可任意分频。-9999 counter
miankao
- module t1 (clk,quot) input clk output quot reg quot reg[23:0] tc always@(posedge clk) begin tc<=tc+1 b1 if (tc==24 h013fff) begin quot<=1 tc<=0 end else quot<=0 end endmodule-module t1 (clk,quot)
dds
- FPGA中用VHDL语言实现的多种波形（正弦、余弦、三角、方波）调制。-modulation by FPGA.
fredivn
- 一段FPGA的分频代码,可以完成FPGA中高频分成低频的功能-a section of code about division of frequency which can cut high frequency to low frequency
SPI
- SPI串行总线接口的VERILOG实现的源代码-failed to translate
searcger
- 序列捕捉器设计，捕捉11010110序列，在捕捉到每个序列后产生一个１时钟周期的标记信号 对捕捉到的序列个数进行计数并输出-failed to translate
VHDL-memory
- 存储器的VHDL描述，包括ROM,RAM,FIFO,stack等多种类型-design of memory by VHDL
feecounter
- 基于FPGA的出租车计费器计费功能的设计，verilog语言。-the function of the taxi‘s feecounter，based on FPGA,using verilog language。