资源列表
DDSVerilog
- Verilog 实现的DDS源码，可以配合NiosII软核使用 -Verilog realization of DDS source, you can use with soft-core NiosII
yedek_son
- a basic Mode Decision hardware for Variable Block Size Motion Estimation in verilog
divider
- verilog divider hardware
GrayCounter2
- gray counter for async FIFO design
i2c_bus
- i2c总线控制器的verilog的实现，编译环境quartus-i2c bus controller verilog implementation, build environment quartusII
1000samples-on-verilog
- 1000个Verilog编写的例程~绝对超值!-Routines written in Verilog 1000 ~ absolute value!
clock_divider
- clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc-clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc
SEG7_Timer
- 七段数码管时钟显示的verilog程序，开发环境quartusII7.0-Seven-segment digital tube display clock verilog program development environment quartusII7.0
clock
- 可调式时钟，可对时钟每位进行加减，被调整位闪烁显示-Adjustable clock, each clock can add or subtract, to be adjust-bit flash display
PWM_LED
- 利用PWM控制LED亮灭的verilog程序，开发环境quartusII7.0-Using PWM control of LED light off a verilog program development environment quartusII7.0
xapp202
- 在ATM应用中实现内容寻址寄存器（CAM）-In the ATM application to achieve content addressable register (CAM)
dds
- 高精度高速正弦波生成，正弦波相位和正弦波频率可调。-make sin