资源列表
QuartusII6.0_cn
- QuartusII6.0简体中文教程.pdf，讲的很详细，共有260页，很好的资料-QuartusII6.0 English tutorial. Pdf, said very detailed, 260 pages, very good information
shuzizhong_vhdl
- 用vhdl语言写的数字钟程序，有兴趣的可以-Vhdl language used to write the digital clock program, interested to see
jiaotongdeng
- 网上虽然有很多交通灯的参考程序,但又么不是很低级,又么没多少扩展功能,这是我写的交通灯程序,绝对超经典!-Although there are many traffic lights online reference program, but Why is not very low, then Why did not the number of extensions, this is the traffic light program I wrote, absolutely super clas
3_8CODER
- module decoder_38(out,in) output[7:0] out input[2:0] in reg[7:0] out always @(in)
USB2_chip
- 交通灯控制 是很好的一个程序 大家支持一次啊，呵呵。-Traffic light control is a good a program we support a ah, huh, huh.
pr_hmm
- ~veterbi算法-~ Veterbi algorithm ~HMM~~~~~~~~~~
matrix3x3
- 3*3矩阵的乘法器代码!!! !!! !!! !!!!1-3* 3 matrix multiplier code~
jiaotongdeng
- 以FPGA为开发平台的交通信号系统，带有倒计时和蜂鸣器功能。-To FPGA development platform for the traffic signal system, with a countdown and the buzzer function.
add
- 自己用verilog写的加法器，时序仿真已经通过-Their own written with verilog adder, timing simulation has been adopted
08-Multiplexers
- vhdl code for adder for quartus
clk_divider
- Simple Clk Divider for FPGA design in Verilog -Simple Clk Divider for FPGA design in Verilog
ds18b20_verilog
- 用verilog语言编写，实现DS18B20测量温度的程序，包括整个工程文件。-Using verilog language, achieve DS18B20 temperature measurement procedures, and including the project file.