资源列表
DE2_CCD
- FPGA 上实现VGA控制器 开发平台为altera官方开发板de2 -DE2 FPGA VGA LCD
communicationFPGADesign
- 包含matlab和Verilog两中代码：主要功能是关于无线通信的-contain：matlab and Verilog codes about communication
viterbi
- 对于语音信号的Viterbi算法的简单仿真实现 在QuartusII下-Viterbi algorithm for speech signals simple simulation to achieve in the next QuartusII
hdlsrc_new
- CIC滤波器实现，级联FIR，节省资源-CIC filter
VGA_test
- 基于FPGA设计的一段测试VGA接口的VHDL小程序\功能为在显示器上间隔显示横条、竖条以及棋盘格等彩条信号，希望对初学FPGA驱动VGA接口的电子爱好者有用-FPGA-based design of a VGA interface VHDL test applet \ functions for the intervals shown in the display bar, vertical bars and checkerboard patterns and other signals of
Soda_Machine
- drink machine finite state machine
fifo.v
- This the source code for FIFO -This is the source code for FIFO
6clock
- verilog 电子表。可显示年，月，日，支持闰年。-verilog electronic form. Displays year, month, day and support a leap year.
vhdl_math_tricks
- VHDL语言中如何使用数据，加减乘除和类型转换，对FPGA进行数值计算的人非常有价值的文章-VHDL language how to use the data, Math, and type conversion, the very valuable article for FPGA numerical calculation
LED
- 实现数码管的秒。分钟位显示。时钟1s调一次，下载到板子，通过验证了的verilog程序-To achieve digital control of the second. Minute digital display. 1s adjusted clock time, downloaded to the board, through the verilog program verified
LD
- verilog语言实现LD灯的轮流点亮，下载到板子，验证了的。下载即可在ISE中实现仿真。-verilog language LD lights turn lights, downloaded to the board to verify the. Downloads can be realized in the ISE simulation.
CLK_5
- verilog实现时钟的奇数分频，通过ISE仿真。-verilog to achieve the odd clock frequency, by ISE simulation.