资源列表
clk_divide
- 实现了一个通用分频器，可以实现任何分频的程序-To achieve a common divider, can achieve any frequency of the procedure
Designing_Multi-Asynchronous_Clock_Designs
- 这里介绍了如何使用多时钟树的方法，这在FPGA中经常用到-This paper describes how to use multi-way clock tree, which is often used in FPGA
LCDdisplay
- 自己编写的LCD显示，已经在自己的板子上试过，完全可以运行-I have written the LCD display, has been tried in their own board, can run
experiment8_only1
- 交通灯实验程序，集成在一个工程里面，VHDL语言编写。我们上课的作业-Traffic lights test procedures, integration in a project which, VHDL language. We are working class
experiment7
- 频率计。我们EDA技术实用教程课程的实验7-Frequency counter. We EDA technology practical course curriculum experiment 7
experiment1
- VHDL实验一，利用原理图输入法设计4位全加器-VHDL test 1, use of schematic input 4-bit full adder design
experiment4_play
- VHDL实验四，设计一个异步清零和同步时钟使能的4位加法计数器-VHDL Experiment 4, an asynchronous reset and synchronous design clock enable 4-bit adder counter
experiment5_1
- VHDL实验5，七段数码显示译码器设计。1）用VHDL设计7段数码管显示译码电路，并在VHDL描述的测试平台下对译码器进行功能仿真，给出仿真的波形。-VHDL Lab 5, Seven-Segment Display Decoder. 1) design using VHDL 7 segment LED display decoder circuit, and the VHDL descr iption of the decoder under test platform for functio
experiment6
- VHDL课程实验6，数控分频器的设计。对应不同的输入信号，预置数（初始计数值）设定不同的值，计数器以此预置数为初始状态进行不同模值的计数，当计数器的状态全为1时，计数器输出溢出信号。用计数器的溢出信号作为输出信号或输出信号的控制值，使输出信号的频率受控于输入的预置数-VHDL course experiment 6, NC Divider. Corresponding to different input signals, the set value (initial count) to set
fpga_led_clock
- 最近用verilog编写的数字时钟显示代码，已在FPGA开发板上跑过。-Recently prepared with digital clock display verilog code ran in FPGA development board.
shuzizhong
- VHDL语言编写的数字钟的模拟程序，可以实现定时，时分秒的显示等-Digital clock written in VHDL simulation process can be achieved regularly, minutes and seconds of display time
ondometer
- 用verilog语言编写的运行与FPGA上的基本的频率计程序，有各种数量级的精度，开发环境为quartus2-ondometer written by verilog