资源列表
s1
- 64路脉冲信号校准装置信号发生器程序，可依序发出64路脉冲信号，脉冲信号以10ms为间隔一次发送-64 pulse signal generator calibration device procedures, in turn emit 64 pulses, pulse interval of 10ms once sent
VHDL_Source
- SLC1657 core，一款兼容PIC16c57的MCU内核代码-SLC1657 core which is well compatible with PIC16C57 microcontroller.
32ADD
- 32位超前进位加法器，verilog hdl代码实现，包含源程序-32 lookahead adder, verilog hdl code, including source code
verilog_DATA_displays
- 使用verilog语言，滚动显示“verilog”字符串程序代码及相关说明-Using verilog language, scrolling display " verilog" string code and instructions
verilog_pics_lvbo
- verilog图像滤波算法源文件，可供图像处理硬件程序参考-verilog image filtering algorithm source files, available for image processing hardware program reference
EPM240_datas_all
- 某同学的verilog学习代码，入门实验，已验证，初学者学习。-A student' s learning verilog code entry experiments verified, for beginners to learn.
RTL
- UART RTL测试程序，用于串口调试，红色飓风E16开发板使用-UART RTL test procedures for serial debugging
JF
- 设计一个小型加法电路，以DE2板上18个拨动开关作为两组输入，代表两组十进制数（1-9），用七段数码管显示两个加数以及输出的和。-Design a small adder circuit to DE2 board 18 toggle switches as two inputs, two representatives of the decimal number (1-9), with two seven-segment digital display and output and the ad
Simple-keyboard-research-
- 简易电子琴简单实现七个音阶的演奏和电路模拟-Simple flower simple implementation and circuit simulation played seven octave
dianzhao_dianzhen
- 使用altera的MAX2系列CPLD驱动16*32的双色点阵屏，包含“空车”，“重车”，“电召”三个字。driver.v文件用cpld驱动了东芝的TC62D748芯片，该芯片常用于扫描点阵的驱动上-The MAX2 series CPLD using altera-color dot matrix display driver 16* 32, with " empty" , " heavy vehicles" , " on-call" in t
FPGA-based-image-compression
- 基于FPGA图片压缩技术的解码算法的研究和实现。-FPGA-based image compression technology research and implementation of the decoding algorithm.
exp3-SignedDivision
- 有符号数除法，用移位法实现，需要Basys2硬件支持，更新了除数为-8的漏洞。-Signed division, achieved by shifting method requires Basys2 hardware support, updated the divisor is-8 vulnerabilities.