资源列表
Verilog-testbench-and-memory-I2C
- verilog编写的测试平台，内含具体project和储存模块的编写-Verilog testbench for digital design Memory I2C module Assignment
DELAY
- 一个用元件实现的延时例程，通过这个例程可以学习元件的使用和简单的计数器延时的编程方法。-A delay routine use components to achieve through this routine can learn to use the elements and simple programming counter delay
key
- 用VHDL编写的一个按键检测的例子，采用了防抖，每按一下按键，输出一个按键脉冲。-Examples of VHDL prepared by the detection of a button, using the image stabilization, each key is pressed, the output pulse of a button.
fir_test01
- 在quartus ii 环境下，用VHDL语言编写的基于ALTERA 的IP核的FIR低通滤波器。 -In quartus ii environment, using VHDL language ALTERA FIR IP core based on the low-pass filter.
Cepin
- 使用FPGA编程器件，实现实时测频功能，语言简单-Frequency measurement
fec_encoder
- This module Implements the Forward Error Correction Encoder
carry-look-ahead-adder32
- This implements Carry look ahead adder in verilog
wallace_tree_multiplier
- this implements wallace tree multiplier in verilog
New-folder
- i have attached area efficient and low power carry select adder and with code
image-new
- this coding is very effectively used for the image compression technique in vhdl
Verilog-Accumulator
- the folder contains two files written by Verilog HDL. the first one is an implementation of an accumulator that takes serial data as an input, and its output will be an accumulated sum of each consecutive four input samples. the second file is a te
booth_mul
- Booth multiplier used for multiplication of 2 s complement numbers in digital design by using booth multiplier we can reduce the partial products by encoding bits in the multiplier and perform the operation according to the encoded results on multipl