CDN加速镜像 | 设为首页 | 加入收藏夹
当前位置: 首页 源码下载 嵌入式/单片机编程 VHDL编程

资源列表

« 1 2 ... .91 .92 .93 .94 .95 3196.97 .98 .99 .00 .01 ... 4323 »
  1. Transmitter

    0下载:
  2. Transmitter
  3. 所属分类:VHDL编程

    • 发布日期:2014-01-25
    • 文件大小:2.17mb
    • 提供者:soorajnp
  1. lcd_rotary_button

    0下载:
  2. Spartan 3E kit. LCD and rotary button example code.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-02
    • 文件大小:850.18kb
    • 提供者:Sodkhuu
  1. sqrtcsla

    0下载:
  2. Carry select adder using square root method.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-16
    • 文件大小:3.6mb
    • 提供者:MITUN
  1. Stage_I

    0下载:
  2. FPGA SPDS for bioimpedance computing
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-23
    • 文件大小:385.16kb
    • 提供者:Shreeyog Nimkar
  1. VmodCAM_Ref_VGA-Demo_13

    0下载:
  2. VmodCam sample, only works with ISE13
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:781.88kb
    • 提供者:angel21
  1. Pipeline_cpu

    0下载:
  2. this file contain descr iption of cpu in VHDL language that implies pipeline fetching.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:2.5kb
    • 提供者:babak aghaei
  1. modeling-pojects

    0下载:
  2. this compressed file basically contains 5 type of cpu simulations in VHDL code. 1. basic cpu 2. pipelin cpu 3. parwan 4. j1 and j2 cpus 5. j1 and j2 with JTSG port
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-05
    • 文件大小:18.81kb
    • 提供者:babak aghaei
  1. LCD in verilog

    0下载:
  2. this is the source code using to operate LCD in DE2 board
  3. 所属分类:VHDL编程

    • 发布日期:2014-01-29
    • 文件大小:8.56mb
    • 提供者:oliver_grim
  1. descode

    0下载:
  2. Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorit
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:5.32kb
    • 提供者:akram
  1. tcdg

    0下载:
  2. Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorit
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:5.32kb
    • 提供者:akram
  1. test-des

    0下载:
  2. Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorit
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-05
    • 文件大小:5.32kb
    • 提供者:akram
  1. min_max_finder_part3_M4

    0下载:
  2. 给定一组数据,从这一组数据中找出他们的最大值和最小值-to get the maximam and minimam of a series of numbers
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1.33kb
    • 提供者:czd
« 1 2 ... .91 .92 .93 .94 .95 3196.97 .98 .99 .00 .01 ... 4323 »
搜珍网 www.dssz.com