资源列表
tr
- VHDL CODE FOR TRAFFIC LIGHT CONTROLLER
johncounter_D
- VHDL CODE FOR JOHNSON COUNTER USING D FLIPFLOP
syncup_dn
- VHDL CODE FOR SYNCHRONOUS UP/DOWN COUNTER
EPM7032-ENCODE
- ALTETRA EPM7032 ENCODE正反轉16位元輸出+14輸入+內碼-ALTETRA EPM7032 ENCODE
Syn_FIFO(wanzheng)
- 基于IPcore的同步FIFO的编写。读写数据位宽都为8bit，深度为32.-Based IPcore synchronous FIFO preparation. Read and write data width are 8bit, a depth of 32.
synchoronous_FIFO(jianban)
- 基于IPcore的同步FIFO的设计。采用Verilog代码书写。读写位宽均为8bit，深度为32.-IPcore synchronous FIFO-based design. Using Verilog code writing. Read and write bits wide are 8bit, depth is 32.
mcsa
- Simple carry select adder
ripple_16
- Ripple carry adder in detail using vhdl
rtl
- 通过verilog实现pc串口和fpga的双向通信。代码是老外写的，非常严谨-the verilog code comnunicate with the pc by serial port
MAC-protocol-based-on-ARM-and-FPGA
- 一种基于ARM和FPGA的可重构MAC协议设计，以及各功能模块介绍-A reconfigurable MAC protocol design based on ARM and FPGA, as well as introduce the functional modules
Protel-dxp-operating-skills-summary
- 详细介绍Protel DXP 操作技巧，包括封装库的设计，原理图的设计-Details Protel DXP operating skills, including package library design, schematic design, etc.
ofdm22
- ofdm modem in vhdl.....................