资源列表
lcd1602_test
- 基础实验07-1602英文字符显示实验-FPGA源代码-Experimental basis 07-1602 English characters display experiment-FPGA source code
buzz_test
- verilog蜂鸣器实验，用于FPGA开发板。-verilog buzzer experiments, for FPGA development board.
sw_seg_test
- 拨码开关输入数码管显示实验，用于FPGA开发板-DIP switch input digital display experiment for FPGA development board
sw_led_test
- 拨码开关输入LED显示实验，用于FPGA开发板-DIP switch input LED display experiment for FPGA development board
bakema
- 产生巴克马发生器 通过计数来决定输出 具有复位功能-Bake Ma produced by counting to determine the output of the generator has a reset function
RX_TX_FIFO
- 完整的串口收发模块 可根据需要在进行重组 处理数据-Complete serial transceiver module during the restructuring process the data as needed
Example18
- 七人表决器，可以实现7个人表决的小程序，计算表决同意人数，根据人数数码管显示表决通过人数-voting for seven people，7 people can vote applet
MY_CAMARA_3_18_FIFO
- 基于QUARTUS集成环境开发的IP核，能够读取数据，并将其显示在数码管上-the IP core of fpga,can be used in embedded device
Example1
- 一款简单的出租车计费器的VHDL小程序，里程小于1Km是显示基价，超过另外计费-A simple VHDL taxi meter is a small program, mileage is a base price of less than 1Km over another billing
Example23
- 设计一款多功能数字秒表的VHDL小程序，产生100Hz时钟的分频计数器-Design a multi-function digital stopwatch VHDL applet, generate 100Hz clock divider counter
Example22
- 设计了一款基于多功能数字时钟的小程序，产生1Hz时钟的分频计数器并正常运行-Based on a small program designed multifunction digital clock divider to generate 1Hz clock counter and running
Example25
- 设计一款基于VHDL的数码锁的小程序，其中加入了数码管显示功能及报警系统-VHDL-based design a digital lock small program, which joined the digital display and alarm system