资源列表
memory_cores
- 包括标准的FIFO的设计以及一种通用的CACHE设计。-failed to translate
Verilog-HDL-Synthesis-=
- Verilog HDL Synthesis A Practical Primer-failed to translate
traffic
- 基于FPGA的交通灯控制系统，使用verilog语言书写，quartus II运行-FPGA—veriliog,Light controlor system
naozhong
- 万年历并且带闹钟功能，时间可调,闹钟可调，还有响铃-failed to translate
cal
- verilog设计计算器顶层模块，无下层模块需自行添加-verilog based calculator
spiV
- FPGA spi通信协议，很全，大家参考，希望对大家有用。-Fpga spi Communication protocol, very full, we refer to the hope that useful.
coregen_overview
- core generator vhdl book
coregen_tutorial
- core generator vhdl book
robust_ahb_matrix_latest.tar
- Advanced high performance bus usin matrix method
mb-tutorial
- core generator vhdl book
dist_mem_gen_ds322_2
- core generator vhdl book
dist_mem_gen_ds322_3
- core generator vhdl book