资源列表
s
- 用VerilogHDL编写的数字频率计（附加显示编码器，可将结果显示在7段数码管上）-With VerilogHDL preparation of the digital frequency meter (additional display encoder can be displayed on the 7-segment LED)
src
- AXI Slave codes in verilog. Downloded from www.opencores.org free download
OUT_Port.tar
- Outport Controller for Globally asynchronous and locally synchronous systems
inverter_schematic.tar
- CMOS inverter Schematic on IC615 Cadence
FSK
- vhdl编写的FSK编码器与解码器，绝对可用，拿去用吧。 -the FSK encoder and decoder VHDL written, absolutely free, and take with you.
lift
- 这是我的短学期的课程设计，用VHDL实现两部三层电梯运行。两部电梯采用联动的运行方式，基本符合条件。并且添加了超载报警系统。希望能帮助到你们。-This is my short semester curriculum design, two three elevator operation using VHDL. Two elevators linkage operation mode, in line with the conditions. The design clear thinking
openverifla_latest.tar
- This is an important file source code regarding the uploaded program title.
lab12
- QuartusII上的有限状态机的工作原理和设计的实现-Finite state machines at QuartusII principles and design
lab11
- 利用几种不同的方式在QuartusII上设计FPGA片上存储器-Using several different ways in the FPGA on-chip memory design QuartusII
digital-clock-VHDL
- 数字电子钟的VHDL硬件描述语言实现，可以用quaturs软件实现。-digital clock based on VHDL
i2c_slave_model
- IIC总线实现源码，调试通过可用，通信用-IIC bus to achieve source code, debugging through the available
16x4-register-VHDL
- 16x4的寄存器的VHDL硬件描述语言的实现，可以用quaturs实现。-16x4 register based on VHDL