资源列表
frequency-meter
- 基于Verilog HDL语言，编写的频率计。-Based on Verilog HDL language, written in frequency meter.
Introduction-to-C-Sharp-classic
- c#编程的经典书籍，.Net开发的最佳伴侣之一-c# programming classic books, Net developed one of the best companion
FPGA_pipeline
- 用Quartus2开发的流水线指令集计算机系统模型，具体指令功能见包内说明-Development pipeline Quartus2 instruction set computer system model, described in the specific command functions, see package
Card_Seller
- 基于VHDL语言的自动电话卡贩卖机的代码，在Altera的Quartus平台上编译通过。-Automated phone card vending machine code, based on VHDL Altera' s Quartus platform, compile.
clk_div
- 用Verilog HDL实现对时钟的四分频和16分频，并在Quartus上仿真-Clock divided by four and divided by 16, and in the Quartus simulation using Verilog HDL
multi_CX
- 实现8*8串行乘法器的verilog源代码，经过调试的哦！-8* 8 serial multiplier verilog source code, after debugging Oh!
ad_da
- 用于ad_da模块的操作，可以作为入门使用-Operation for ad_da module can be used as an entry
multi_4bits_pipelining
- 实现4*4流水线乘法器的verilog源代码，在FPGA板上运行-4* 4 pipelined multiplier verilog source code, running on the FPGA board
PLL
- FPGA板上的锁存器PLL控制代码（verilog代码）-FPGA board latch the PLL control code (Verilog code)
RAW2RGB
- 图像由RAW向RGB格式转换的verilog源代码实现-Images from the RAW format to RGB conversion Verilog source code implementation
RGB2YCbCr
- 图像转换的verilog代码（RGB图像转换为YUV图像）-The image conversion Verilog code (RGB image is converted to YUV image)
Sdram_Control_4Port
- SDRAM控制器的verilog源代码实现-SDRAM controller Verilog source code to achieve