资源列表
VHDmimasuo
- 用VHDL编写的具有如下功能的电子密码锁：输入为八位二进制的电子密码锁 输入正确，开锁灯亮，输入错误，开锁警示灯亮，同时发出报警声音，按下复位键，报警消失，具有密码修改功能-Prepared using VHDL has the following features of electronic code lock: eight binary input to enter the correct electronic code lock, unlock lights, wrong, unloc
veriloghdl
- Verilog HDL是一种硬件描述语言，用于从算法级、门级到开关级的多种抽象设计层次的 数字系统建模。被建模的数字系统对象的复杂性可以介于简单的门和完整的电子数字系统之间。数字系统能够按层次描述，并可在相同描述中显式地进行时序建模。-Verilog HDL is a hardware descr iption language, used from the algorithm level, gate-level to switch level design of a variety of
EDA_12
- usb blaster by zliang
uart1
- RS232(UART)串口传输，通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx
TSE_MAC_standalone_rar
- MAC层接口标准 verylog HDL 语言-MAC layer interface standard using verylog HDL language
XAUI-Hspice[1]
- 10G 附属单元接口 （ standard for XGMII） 的实现-10G Attachment Unit Interface realized by hspice
test4
- 用 vhdl 语言实现的 32个 条目的 ARP-using vhdl language to realize ARP protocol with 32 entries
GenIO
- ucf genio should be helpfull for beginers
VerilogHDL(1-7)
- verliog程序的教程和一些实例方便学习-verliog program tutorials and examples to facilitate learning
VerilogHDL(8-10)
- verliog程序的教程和一些实例方便学习-verliog program tutorials and examples to facilitate learning
VerilogHDL(11-13)
- verliog程序的教程和一些实例方便学习-verliog program tutorials and examples to facilitate learning
hdb3
- hdb3编码源程序完整版，内含插B，插V程序，功能完整，欢迎下载-library ieee use ieee.std_logic_1164.all entity hdb3 is port(codein: in std_logic clk : in std_logic clr : in std_logic --复位信号 codeout: out std_logic_vector