资源列表
sc
- 密码锁 可以输入密码 并 进行密码比较，三次错误密码即锁定并报警-Lock can be password and the password comparison, the wrong password three times the lock and alarm
in_out_put
- 双向RAM的Verilog程序，能实现双向传数据-The Verilog bidirectional RAM process, to achieve a two-way mass data
3_3_mean_diltter(ALU)
- 3*3均值滤波的VHDL语言实现的工程，对红外图像进行有效的去噪处理。这是其中的ALU模块，专门用来测试其延迟状况的模块。-3* 3 mean filter VHDL language works effectively on the infrared image denoising. This is one of the ALU module, designed to test the status of the module delay.
FINAL
- MESSENGER BETWEEN 2 FPGA WITH PS2 KEYBOARD CONTROLLER AND VGA CONTROLLER USING SERIAL TRANSMISION
qiangdaqi
- 本程序为四路抢答器verlog HDL语言工程实例。-This program is four Responder verlog HDL language engineering examples.
asynchronous-fifo
- 同步fifo的调用程序，调用Quartus II 9.0 (32-Bit)中的fifo模块-Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module
256FFT
- 256 point FFT Implemention
yunlei
- 实现出租车计费系统，包含所有的源文件-Taxi billing system to achieve
UART_RX
- 这是借鉴别人的带有FIFO的Verilog代码分享给大家，共同学习-This is learn from others with FIFO Verilog code for everyone to share, learn together
LPT_Parallel_Receiver_Alon_and_Julia_Final
- A project in VHDL for Parallel Receiver
Modelsim-functional-simulation
- 介绍了Model Technology 公司的Modelsim XE II v5.6e的主要结构、属性设置、Modelsim XE II v5.6e与ISE5.2的软件接口，测试激励文件的建立以及Modelsim仿真分析方法。Altera公司QuartusII3.0仿真器(Simulator) 的主要结构、属性设置以及仿真分析方法。 -Introduced the Model Technology Modelsim XE II v5.6e company' s main struct
FPGA_radar
- 优秀硕士论文，基于FPGA的雷达信号模拟器设计，对学FPGA的，特别是学雷达的同学有很好的参考价值-Outstanding master s thesis, based on radar signal simulator FPGA design, FPGA-on study, in particular the study of radar has a good reference Student Value