资源列表
FPGA-Uart
- fpga串口通讯程序。用Verilog语言编写-fpga serial communication program. Verilog
卷积交织器解交织器设计
- 交织技术通常分为分组交织和卷积交织。分组交织过程是数据先按行写入，再按列读出；解交织过程是数据先按列写入，再按行读出。其特点是结构简单，但数据延时时间长，而且所需的存储器比较大。(Interleaving techniques are usually divided into packet interleaving and convolution interleaving. Packet interleaving process is the first data written by row,
at7_ex05
- 实现PC端通过UART发送数据到FPGA，FPGA将所接收到的数据同样是通过UART原本不动的发回给PC端。(The PC terminal sends data to FPGA through UART. FPGA sends the received data back to the PC end by UART.)
DS18B20
- 基于18b20的温度计，已编译成功，VHDL语言编写，亲测可用。-18b20-based thermometer, compiled successfully, VHDL language, pro-test is available.
experiment1
- 这是一个并行的流水灯代码,实现一个流水灯的功能-This is a parallel light water code to achieve a water lights function
altera_ddr_verilog
- altera的DDR控制器源码（包括仿真与说明文档），DDR为mt46v4m16，Verilog-The DDR controller source of altera (including simulation and documentation), DDR is mt46v4m16, Verilog
ref-ddr-sdram-verilog
- ddr_sdram开发参考verilog建模-ddr_sdram with verilog
ledwalk
- FPGA入门系列实验教程——跑马灯,让实验板上的8个LED实现跑马灯的功能-FPGA Starter series of experiments tutorial- Marquee experimental board 8 LED Marquee
3.VGA
- fpga控制VGA显示的verilog程序，已经测试-fpga VGA display control program, has been tested
4fsk-Verilog-HDL
- 基于Verilog HSL的4psk调制解调-very nice
PSTOLCD
- 此为在xinlix系统上开发的PS通信程序，用VHDL语言开发-This xinlix system in the development of PS communication program, with the development of VHDL language
jianpan_and_shumaguan
- 矩阵键盘4*4（必须有上拉电阻），已消抖，可直接用。-4* 4 matrix keyboard (must have pull-up resistor), has debounce, can be directly used.