资源列表
division
- Verilog n-bit Division using datapath and controller for COMPUTER ARCHITECT LAB-Verilog n-bit Division using datapath and controller for COMPUTER ARCHITECT LAB
Verilog
- verilog_hdl教程135例 非常实用的入门程序-verilog_hdl Tutorial 135 cases
Desktop
- 基于FPGA的频率计设计 源代码+论文 绝对好用-The frequency meter design based on FPGA source code+ thesis
CPUdesign
- 计算机组成原理实验多时钟周期CPU设计，包含VHDL代码的设计，实验电路图，实验详细截图。-Computer component experiments designed more CPU clock cycles, including VHDL code design, test circuit, test detailed screenshots.
lqx_fsk_ok
- 模块化实现2FSK调制,简单易懂非常适合初学者学习参考.-Modular realization 2FSK modulation, easy to understand reference is suitable for beginners to learn.
0133
- 实现电子时钟功能，能够设置时间，最大时间精确度为0.01s-eletronic clock
abc
- 关于七段译码管的源程序，对于制作可编程元器件有一定帮助。-On the seven-segment decoding control of the source, for the production of programmable devices will definitely help.
RISC_CPU
- Verilog写的简单处理器QuartusII下可编译 //指令 操作码 源寄存器 目的寄存器 操作 // NOP 0000 xxxxx xxxxxx 空操作 //ADD 0001 src dest dest<=src+dest //SUB 0010 src dest dest<=dest-src //AND 0011 src dest dest<=src&&dest //NOT 0100 src dest dest<
lab9_Verilog
- VERILOG 经典实验 简单的处理器 外国实验PDF文档 内附详细说明 -VERILOG 经典实验 简单的处理器 外国实验PDF文档 内附详细说明
H[mm.264
- 这是一个描述的文档，教你怎么写Verilog关于H264 的文章那个，考了非常受启发。-This is a descr iption of the document, teach you how to write Verilog that the article on the H264, the test is very enlightening.
arraymultiplier
- vhdl code,about arraymultiplier,fixed point
FPGA
- fpga在步进电机驱动上的应用实例及代码-fpga stepping motor drive in the application example and the code