资源列表
CLanguageProgrammingForTheDevelopmentOfThoseGuidel
- 本文举例说明了如何用软件实现脉宽调制(PWM)，如何将该设计转换成一个可以在FPGA中运行的逻辑块，并能利用存储器映射I/O接口通过软件完成对该逻辑块的控制。- the paper illustrates how to use software pulse width modulation (PWM), how can the design into a run in the FPGA logic blocks, and can use memory mapped I/O Interface c
MyDDS
- 利用查找表法编写的DDS的verilog程序，节省了利用IP核实现需要的资源，软件为ISE，-Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
Average
- 利用ISE软件编写的求平均数的verilog程序，可以用来求平均数，用来对信号幅度的平均值进行计算-ISE software written request using the average of the verilog program can be used to seek the average used to calculate the average amplitude of the signal
Kaifang
- 利用ISE编写的实现开方功能的verilog程序，利用了CORDICIP核，可以完成开方功能-Prepared using ISE verilog program to achieve prescribing functions, using the CORDICIP nuclear, prescribing functions to be completed
d-flip
- 同步复位的D 触发器，该触发器有一个数据输入端D，时钟输入端CLK，清 零输入端CLR，数据输出端Q。CLR为1时，触发器复位-Synchronous reset D flip-flop, the flip-flop has a data input D, the clock input CLK, clear input CLR, the data output Q. CLR 1, the trigger reset
VHDL
- VHDL语言程序设计及应用的源代码。包括2-12章的内容。内有一个应用实例：数字密码引爆器的设计。-VHDL language and application programming source code. Including the contents of Chapter 2-12. There are a practical example: the design of digital code detonator.
traffic_light
- 交通灯的实现，南北和东西行车，有通车剩余时间。有仿真图-Implementation of traffic lights, north-south and east-west road, there is the opening of the remaining time. A simulation map
clock
- 数字钟VHDL源程序，有仿真图，源代码-VHDL digital clock source, there are simulation plans, source code, etc.
sin_generator
- Sin Generator. 16 points on period.
reed_solomon_decoder_latest.tar
- reed solomon (204,188). in verilog.
rs_dec_enc_latest.tar
- Reed-Solomon (255,251). in VHDL.
my_reg
- D触发器，Verilog实现，配有实验说明文档。-D flip-flop, Verilog implementation, with experimental documentation.