资源列表
Vedio_FPGA
- 基于FPGA和SOPC的视频图像处理，视频编解码，系两篇硕士论文，其中一篇需要用CAJ阅读器打开-FPGA and SOPC based on video image processing, video codec, two master' s thesis, Department, of which a reader needs to open with CAJ
VHDLcodes
- Behavioral descr iption of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral descr iption of ALU, RAM MODULE,
FFT_128_floating_point
- 基于Altera FPGA 的FFT128浮点运算模块(veriolg HDL+C51) (开发环境：KeilC51+Quartus7.2）-The module of 128 floating-point FFT based on Altera FPGA(veriolg HDL+C51) （Development environment：KeilC51+Quartus7.2）
AD_DA_Chip_test_program
- AD DA芯片测试程序 (开发环境keilC51+Quartus7.2)-AD DA Chip test program (Developmentenvironment： keilC51+Quartus7.2)
signal_generation
- 信号发生模块 开发环境：keilC51 Quartus7.2-Signal Generation Module Development Environment: keilC51 Quartus7.2
DDS_generation
- 基于Altera FPGA的DDS 模块 - DDS generation module based on Altera FPGA
Frequency_Measurement
- 测频程序 C51 Verilog HDL-Frequency Measurement C51 Verilog HDL
8bit_upDown_counter
- a simple 8 bit up/down counter, very handy and optimized
behavioral_counter
- a simple behavioral counter handy for delay counters
interrupt_FSM_for_picoblaze
- finite state machine interupt handler for xilinx spartan 3E
QuartusII
- 概述了可编程逻辑设计中Quartus II 软件的功能。解释软件的功能以及这些功能如何帮 助您进行 FPGA 和 CPLD 设计。-It introduces the funcion of the Quartus II software.