资源列表
mp
- ppm modultion by vhdl
report
- ppm modulation by vhdlcod
RS422_receiver
- UART--异步串行通讯 接收逻辑 （Verilog）16倍时钟接收-verilog--A UART Receiver 16 clock
vhdldesign
- vhdl设计，可以自学vhdl语言后做一些简单的vhdl设计！-vhdldesigning
EDA3
- 该程序是一个带记数使能，异步复位，带进位输出的增一 二十进制记数器，记数结果由共阴极七段数码管显示-The program is a band count enable, asynchronous reset, into digital output by 12 decimal counter, counting the results from the common cathode seven-segment LED display
eda2
- 一个带记数使能，同步复位，带进位输出的增一 六位二进制记数器，记数结果由共阴极七段数码管显示-One with a count enable, synchronous reset, into digital output by 16 binary counter, counting the results from the common cathode seven-segment LED display
93317478verilog.HDL.examples
- hdl代码的相关应用，里面还附有相关实例和介绍说明 -hdl code related applications, which also introduced with examples and instructions related
keyscan_test
- 针对机械式按键存在的抖动问题，用verilog HDL编写了一个采用防抖方案并对按键次数计数的模块，已经在ISE综合通过！-Keys exist for mechanical jitter, with verilog HDL prepared a program with anti-shake button and count the number of modules have been integrated by ISE!
testbench
- altera 最新的CYCLONE IV的pci-e核的testbench，VHDL源程序。-altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.
watchver_cr2
- Stopwatch example -Stopwatch example !!!!!
vgaChars
- 有关vhdl的硬件实现VGA设计的代码。 -This is a tutorial on how to create proper 640x480 vga output using the altera UP2 development board.
DE2_TV
- 友晶公司DE2开发板的TV示例完整源代码 FPGA Cyclone-Friends of the crystal of TV company DE2 development board complete source code for FPGA CycloneII sample