资源列表
61EDA_D825
- 该设计针对SMB总线进行的控制操作，包括控制，接口及仿真文件-THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, N
verilog_logic
- 基本逻辑运算，Verilog实现，带有实现教程。-Basic logic operations, Verilog implementation, with the realization of tutorials.
divide
- 关于verilog的分频程序 等占空比 非等占空比 小数分频 奇数分频-Verilog frequency on the sub-procedures such as the duty cycle of non-duty-cycle fractional odd frequency, etc.
VHDLExamples
- VHDL例子，是初学者很好的教程，很不错的-VHDL example is a good tutorial for beginners, very good
17869318fpga-example1
- FPGA实例包含UARTverilog TLC7524接口电路程序 TLC5510 VHDL控制程序 DAC0832 接口电路程序 LCD控制VHDL程序与仿真等-FPGA interface circuit examples include UARTverilog TLC7524 TLC5510 VHDL process control procedures procedures DAC0832 LCD control interface circuit and simulation of V
53607892SRAM_2
- SRM程序，好东西啊。都看看吧-SRM program, a good thing ah. Ha ha ha, look at it
DC_ASSIGN
- counter clock vhdl file for useful to dc compilier
VerilogFPGAUSB
- 用Verilog（FPGA）实现USB源代码大家-Using Verilog (FPGA) source code we look to achieve USB
async_uart
- 用verilog写的串口接收发送通信程序，已经在cyclone EP1C12Q240C8调试通过-Serial receiver with verilog send written communication procedures, has been adopted in the cyclone EP1C12Q240C8 debugging
DE2_70_CAMERA_v1.0.2
- 應用程式verilog相關事件，參考文件-Verilog application related events, refer to documents ... etc.
prathap
- a difficult technique compact programs in verilog-a difficult technique compact programs in verilog..
leapyear
- 在Xilinx ISE软件下关于瑞年计数器的工程，可以判断某一年份是否为瑞年。包含代码及测试代码，已经通过编译，综合，仿真波形完全正确。-Under the Xilinx ISE software counters on the Swiss-year project, can determine whether a given year in Switzerland. Contains code and test code, has passed compiled, integrated, si